FPGA Quality Assurance Engineer needed for Wireless Networking and Security company in the Baltimore area. Base salary $120,000 to $140,000, Employee Incentives, 100% Employer-funded CareFirst Open PPO, Employer-funded Health Savings, and 401(k) match.

This Jobot Job is hosted by: Patrick Murray
Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume.
Salary: $120,000 - $140,000 per year

A bit about us:

Based in Maryland, our company offers the world’s only fundamentally secure means of wireless communication. Our modulation can be implemented as a block of logic in an SDR, FPGA, or ASIC technology and gives innovators across a host of industries the next generation of secure wireless systems.

Our mission is to make the connected world more safe and more secure. We are currently seeking a FPGA Quality Engineer with experience in OVM/UVM or VHDL. The FPGA Testing Engineer will be a key contributor in out technologies moving forward.

Sounds interesting? Please apply to the Test Engineer FPGA position today.

Why join us?

As an FPGA Verification Engineer with out company, we can offer:
 

• $120K-$140K Expected Base Salary
• 100% Employer-funded CareFirst Open PPO
• Employer-funded Health Saving Account
• 401(k) Plan with Employer Matching Contributions
• Employee Incentive Program
• All Federal Holidays and Generous PTO

Job Details

Responsibilities for the FPGA Test Engineer:
 

• Design and maintain testing infrastructure for our FPGA development organization
• Develop bus functional models (BFMs) to aid in simulation and reduce code duplication
• Create test suites leveraging industry standard testing frameworks (UVM/UVVM or equivalent)
• Work intimately with FPGA Design Engineers and DSP Engineers to troubleshoot test failures and to aid in creating new tests
• Make use of existing options for connecting test suites to MATLAB golden reference models to validate HDL
• Leverage EDA simulation tool features to create testing metrics such as code coverage percentage, failure reports, etc.
• Create hardware-in-the-loop tests to validate that designs work in hardware

Minimum Required Qualifications:
 

• Experience performing FPGA design verification using SystemVerilog with OVM/UVM or VHDL with UVVM/OSVVM
• Strong background in Cadence Xcelium or Incisive simulators
• Proven ability to work with FPGA module developers providing feedback to address discovered issues
• Ability to work in a Linux only environment
• Experience using VPI (Verilog/SystemVerilog) or FLI (VHDL) to interface with C/C++ golden models
• Experience using Tcl to automate EDA tools such as Cadence Xcelium, ModelSim, Vivado, Quartus, etc.
• Experience writing and taking action on test plans for FPGA/ASIC designs
• Expert in common problem areas of FPGA designs such as CDC, HDL language edge cases, and bugs in standard protocols (AXI, AXIS, AMBA, etc.)

Nice to have:
 

• Experience using formal verification tools
• ASIC verification experience
• Experience testing with hardware-in-the-loop
• Experience using software development life cycle (SDLC) principles for testing
• Experience using Git for revision control
• Vivado and/or Quartus expertise
• Experience using TeamCity (preferred) or Jenkins for CI/CD
• Experience using Python for task automation
• Digital signal processing background
• C/C++ development experience
• MATLAB HDL Verifier and FPGA-in-the-Loop experience

Find your favorite job now by visiting our jobs page